Developped Optimization Algorithm for placement of electronic blocs on automated design tools for electronic circuits
Hand made custom design of chips

Next-Gen Node Exploration: Specialized in standard cell design exploration for N2 Nanosheet nodes, focusing on the characterization of high-performance combinatorial logic and sequential latches.

Algorithm Development: Architected a high-accuracy characterization algorithm for $T_{setup}$ and $T_{hold}$ timing constraints, achieving precise alignment with PDK model expectations.

Silicon Validation: Proven performance reliability, with simulation results and timing models successfully validated against taped-out silicon behavior.

Advanced SPICE Modeling: Mastered complex SPICE simulation environments to analyze transistor-level physics, bridging the gap between architectural intent and physical implementation.

Physical Debugging: Leveraged deep understanding of device physics to identify and resolve critical mismatches between layout parasitic effects and circuit performance.